1. Field of the Invention
The present invention relates to data processing systems, and more particularly to apparatus for store rounding in the floating-point unit of a microprocessor.
2. Background Art
The above referenced patent application Ser. No. 860,987 describes a floating-point unit of a microprocessor. A register file is provided for storing floating point numbers that are in the form of sign, exponent and mantissa. Numbers are operated upon within an adder, multiplier and divider in an internal precision form giving an unrounded result. Prior to storing the result in the register file, it must be rounded and converted to single precision, double precision or double extended precision as chosen by the user. After the result is a written to the register file the user will typically write the result to memory in either single, double or extended precision. When numbers are written to the register file the mantissa may be rounded to one of the three precisions, but the number actually appears in the register file in internal precision. Thus, when a store to memory is performed the number must be rounded and converted to a chosen target precision. Even though the register file holds internal precision numbers, they always fit within the extended precision range and therefore no rounding is needed for extended precision writes. Rounding is only needed for single and double precision writes.
In the prior art, the various steps required are performed sequentially. First the mantissa is rounded, and a new rounded mantissa is generated. If there is a mantissa overflow, an overflow logic shifts the mantissa right to normalize the number. The exponent is then incremented by one to get the next order of magnitude for the number, because if the mantissa is shifted one order of magnitude lower, the exponent has to be incremented to one order of magnitude higher. Then the number is converted to the target precision. In the past, this conversion included a time consuming add to re-bias the exponent. In addition, overflow and underflow must be detected. This sequential process is slow, requiring more than one clock cycle.
It is an object of the present invention to provide a floating-point-unit in which the rounding and conversion of a sign, exponent and mantissa in extended or internal precision format to a single or double precision floating-point number is performed in one clock cycle.